Issue: Feb 2017


Addressing the challenges of designing autonomous vehicles



by Nick Palmen

With the advent of semi and fully-autonomous vehicles comes increasing numbers of sensor clusters, computing power, car-to-car and in-vehicle communication technology, high-bandwidth Ethernet networks, as well as multiple high-definition displays being fitted to cars and trucks.

For automotive suppliers, this shift creates new design challenges to accommodate more complex electronic systems, functional safety, space constraints, power and weight (emissions), and cost. For vendors like Cadence, these changes in the automotive world are opening up new opprtunities.

Automotive Industries (AI) asked Robert Schweiger, Director, Automotive Solutions at Cadence what drives the company’s involvement in the ADAS market.

Schweiger: Cadence has a long history in automotive. Most automotive chips like microcontrollers and airbag chips are mixed-signal devices, for which we’ve been providing the leading IC design flow via our Virtuoso Analog Design Environment. However, over the last couple of years, we’ve seen  major disruption in the automotive sector, mainly driven by the desire to enable autonomous driving. Today, cars are equipped with lots of sensors and cameras, both of which produce a huge amount of data that needs to be processed and analyzed. The traditional microcontroller-based discrete ECU design won’t work for such ADAS ECUs anymore. Processing all of this data in real-time requires a highly integrated ADAS system based on high-performance, low-power SoCs (systems on a chip). Furthermore, developing and verifying such a system calls for new tools, methodologies, and IP. With our broad portfolio of software, tools, and IP we are enabling our customers to master the challenges of designing and verifying a variety of automotive components, sub-systems and, really, the entire system.  AI: How does this affect the automotive supply chain?

Schweiger: OEMs need to introduce a whole range of new technology like smart stereo cameras sitting behind the rearview mirror. Inside the camera system, a convolutional neural network, or CNN, runs on an ADAS SoC for object detection and tracking. The challenge is to develop, verify and optimize such a hardware platform running these complex CNN algorithms before the real chip is available.

The Cadence System Development Suite supports exactly this type of hardware/software co-verification including an advanced debugging environment.

For example, with the Cadence Palladium emulation system, the semiconductor vendor can verify the SoC to ensure that it is working according to spec and start early with the development of software drivers and firmware. The Tier 1 supplier can stream in video sequences of real traffic situations to test the complete ADAS system. The software engineer at an OEM might be interested only in validating and optimizing his algorithm or debugging specific traffic situations, where the applied algorithm did not correctly recognize some traffic signs. The solutions within the System Development Suite support each of these scenarios.

AI: What are some key automotive innovation areas driving the design of SoCs?

Schweiger: ADAS requires video and radar processing, sensor fusion, and car-to-car communication. Infotainment systems need audio sound processing, augmented reality, and smartphone integration. Another innovation area, in-vehicle networking, requires a domain-based distributed architecture, automotive Ethernet backbone, and the ability to connect a variety of sub-systems, including ADAS and the infotainment system.

As the design of infotainment systems has become more complex to meet consumer demand for innovative features, Cadence has helped manufacturers with the design and  verification of chips, boards, and systems that make these systems possible. Cadence also offers a wealth of proven, tested IP that can speed the design cycle and reduce the cost for scalable infotainment systems. As an example, besides the AM/FM analog radio, there are five different digital radio standards worldwide that OEMs need to support. By leveraging a software defined radio (SDR) architecture, the carmaker can use the same hardware platform with an integrated receiver that runs different software stacks to support all radio standards. At the core of the SDR hardware, you will typically find a Tensilica baseband processor doing the software demodulation in combination with a Tensilica HiFi DSP, which is doing the audio decoding (all configurable via software).

The infotainment system has become more and more “abused” for non-typical infotainment tasks such as active noise cancellation, noise vibration harshness and for engine sound design. All of these functionalities can be handled with our Tesilica HiFi Digital Signal Processor (DSP).

In May, we launched our new Tensilica Vision P6 DSP. It is our highest performing vision/imaging processor for the fast-growing vision/deep learning applications areas. The new DSP targets CNN applications, which are dominated by available multiply-accumulate (MAC) performance. Compared to commercially available GPUs, the Tensilica Vision P6 DSP can achieve twice the frame rate at much lower power consumption on a typical neural network implementation. It implements on-the-fly data compression to sharply reduce memory footprint and bandwidth requirements for demanding “fully connected” neural network layers.

AI: What is the impact of ADAS on the in-vehicle network?

Schweiger: ADAS systems need to continuously process a huge amount of sensor data, fuse it together and communicate in real time with other ECUs. Automotive Ethernet, including time-sensitive networking (TSN), enables such deterministic high-speed communication within the vehicle. Cadence provides an Automotive Ethernet media access controller (MAC) IP with audio/video bridging and TSN support that can be integrated into any automotive chip to enable deterministic high-speed  communication up to 1 GBit/s for safety-critical systems. Our MAC IP supports standard interfaces like the Media Independent Interface (MII) to connect an external Automotive Ethernet PHY such as the 100BASE-T1 PHY. Last, but not least, in order to create a complete Ethernet network, there is also an n-port switch IP available that enables designers to integrate a switch directly on a SoC (e.g. with a two-port switch, you can daisy-chain several devices and may save an external switch ECU).

AI: How do you ensure that the ADAS systems are working safely?

Schweiger: An ADAS system is by definition a safety-critical system. Since the ADAS system is actively controlling certain safety-critical functions like acceleration, braking and steering, you’d better be sure that all systems do not unexpectedly fail if a fault occurs somewhere in the car. Cadence has developed tools and flows that allow designers to inject faults into the system and simulate how the system, including its safety mechanisms, reacts to such faults. As an example, you could inject a fault in the memory sub-system of the ADAS SoC to check if your software stack is crashing or a safety mechanism like ECC is able to detect and handle the fault. At the end of the day, you want to know if you have undetected dangerous faults in your system and be able to take care of them.

AI: How do your tools and methodologies help your customers with their safety-critical designs?

Schweiger: Meeting functional safety requirements can be time-consuming, as designers need to stay up-to-date with the latest safety standards and ensure that their design has checkers (to monitor systems and trigger error recovery features) and redundancy (for continuous function even if an error occurs). Safety engineers need to be able to implement requirements tracing from the system to components, and also make sure that their development flow aligns with tool confidence level (TCL). Cadence offers a functional safety solution that helps engineers meet traceability, safety verification, and TCL requirements of ISO 26262. Our solution is built on our Incisive verification platform, and has demonstrated the ability to reduce the ISO 26262 compliance effort by 50%.

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